1. Field of the Invention
This invention relates to generation of clock signals for electronic devices.
2. Description of the Related Art
Electronics devices utilize clock signals to control operation of, e.g., synchronous digital circuits. Clock signals have commonly been generated using crystal oscillators and phase-locked loops. More recently, digital interpolative synthesis has been utilized as described in U.S. Pat. No. 7,417,510. In such an approach, a reference clock is divided by a fractional-N divider, and jitter introduced by the fractional-N divider is reduced by interpolating the output of the fractional-N divider based on the digital quantization error generated by the delta sigma modulator used to control the fractional-N divider. One approach for the interpolation was to interpolate between various phases of the output from the fractional-N divider in order to reduce jitter. In an alternative approach a half clock reference was used to give the interpolator more time to computer interpolated edges since the dynamic range is halved. However, various prior art approaches may have a long absolute delay through the interpolator or require precise duty cycles of the reference clock.